Parse ANSI parameters declaration #1160
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nickg
reviewed
Feb 12, 2025
src/lexer.l
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| @@ -505,6 +505,7 @@ BEFORE ?i:before | |||
| <UDP>{UDP_EDGE} { yylval.i64 = yytext[0]; return tUDPEDGE; } | |||
| <UDP>{UDP_INDICATOR} { yylval.str = xstrdup(yytext); return tUDPIND; } | |||
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| <*>"#(" { TOKEN(tHASHLPAREN); } | |||
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I don't think #( is a single token. It's shown with a space between it them the grammar in the standard (e.g. page 1138 of 1800-2017) and also here:
https://www.sigasi.com/tech/systemverilog.ebnf/#module-parameters-and-ports
Icarus Verilog and Verilator also both treat the # and ( as separate tokens.
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Ok thanks for the review I wasn't aware that they were separate tokens, I'll try to look better into the syntax and adjust the code. It's gonna take a bit of time though
src/vlog/vlog-parse.c
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| static void p_list_of_param_declarations(vlog_node_t mod) | ||
| { | ||
| // parameter_port_list ::= ansi_param_assignments { , ansi_param_assignments } |
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I'm using the System Verilog grammar rather than the traditional Verilog one
nickg
approved these changes
May 30, 2025
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Add changes to parse parameters inside
#()for a module declaration.